The present invention relates to a high-speed semiconductor memory device, and more particularly to a clock data recovery (CDR) circuit, which can recover a distortion occurring during high-speed signal and data processing within a semiconductor memory device and a method for operating the same.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as data storage. The semiconductor memory device outputs data corresponding to an address received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells selected by an address inputted together with the data.
As the operating speed of the system is increasing and a semiconductor integration technology advances, the data processor requires the semiconductor memory device to input/output data at higher speed. In order for the semiconductor memory device to operate faster and more stably, a variety of internal circuits must be able to operate at high speed and transfer signals or data therebetween at high speed.
To apply the semiconductor memory device to high-speed systems, an interface speed for signal or data transfer has also increased. A clock data recovery (CDR) method is used in the semiconductor memory device in order to prevent malfunction and unstable operation caused by signal or data distortion due to noise or interference during an interface operation.
To obtain reliability in transferring signals or data at high speed, the semiconductor memory device uses a CDR circuit. The CDR technology is essentially adopted in high-performance systems and recovers data and clock that were distorted or changed upon transmission by noise and interference.
The transmission of data and clock may be delayed for several reasons on data and clock transmission paths within the semiconductor memory device. This delay obstructs the process of receiving data and clock and performing corresponding operations, resulting in malfunction of the semiconductor memory device. To prevent the malfunction of the semiconductor memory device, internal circuits of the semiconductor memory device perform their internal operations in synchronization with an external reference clock. Thus, when a phase of the reference clock does not coincide with a phase of an internal clock used in the internal operations, the internal circuits of the semiconductor memory device must be controlled according to the detection result of the phase difference. For example, the phase of the internal clock is changed, or the internal circuits perform their internal operations as a current state of the internal clock is considered.
The CDR circuit includes a phase comparator for detecting a phase difference between the reference clock and the internal clock, and a filter for filtering the detected phase difference to output the detection result.
FIG. 1 is a block diagram of a conventional CDR circuit.
Referring to FIG. 1, the CDR circuit includes a phase comparator 110 and a digital filter 100. The digital filter 100 includes a lagging digital filter 100A and a leading digital filter 100B.
The phase comparator 110 compares a phase of an external reference clock REF with a phase of a feedback clock FB used for controlling an internal operation. The phase comparator 110 outputs a phase leading signal PD_EARLY when the phase of the feedback clock FB leads the phase of the reference clock REF, and outputs a phase lagging signal PD_LATE when the phase of the feedback clock FB lags behind the phase of the reference clock REF.
More specifically, the lagging digital filter 100A receives the phase lagging signal PD_LATE for predetermined periods and outputs a lagging state signal LATE when the phase of the feedback clock FB continue to lag behind the phase of the reference clock REF for a predetermined time. The leading digital filter 100B receives the phase leading signal PD_EARLY for predetermined periods and outputs a leading signal EARLY when the phase of the feedback clock FB continue to lead the phase of the reference clock REF for a predetermined time.
The lagging digital filter 100A includes a lagging adder 120A, a first state holding unit 140A, and a lagging determining unit 160A. The leading digital filter 100B includes a leading adder 120B, a second state holding unit 140B, and a leading determining unit 160B. Since an internal structure of the lagging digital filter 100A is similar to that of the leading digital filter 100B, the following description will be focused on the lagging digital filter 100A.
The lagging adder 120A adds the phase lagging signals PD_LATE received for predetermined periods. In this embodiment, the lagging adder 120A is implemented with a 3-bit adder that adds the phase lagging signals PD_LATE received for 8 periods of the reference clock REF. The first state holding unit 140A receives a lagging sum signal SUM_LATE<0:2> corresponding to an addition result of the lagging adder 120A and feeds back a lagging information signal LATE_COM<0:2> to the lagging adder 120A in response to the reference clock REF. When the addition of the phase lagging signals PD_LATE received for 8 periods of the reference clock REF is completed, the lagging determining unit 160A outputs the lagging state signal LATE according to the lagging information signal LATE_COM<0:2>.
FIG. 2A is a circuit diagram of the phase comparator 110 of FIG. 1.
Referring to FIG. 2A, the phase comparator 110 may be implemented with a flip-flop. The flip-flop outputs the phase lagging signal PD_LATE or the phase leading signal PD_EARLY according to the phases of the feedback clock FB and the reference clock REF.
FIG. 2B is a block diagram of the lagging adder 120A of FIG. 1.
Referring to FIG. 2B, the lagging adder 120A includes three 1-bit adders 122, 124 and 126. The lagging adder 120A sums the phase lagging signals PD_LATE successively received eight times to output the lagging sum signal SUM_LATE<0:2>. Reference symbols CA1 and CA2 outputted from the adders 122 and 124 represent a carry. Since the lagging adder 120A for summing the 3-bit signal and the 1-bit signal, that is, the lagging information signal LATE_COM<0:2> and the phase lagging signal PD_LATE, is well known to those skilled in the art, detailed description thereof will be omitted.
FIG. 2C is a circuit diagram of the first state holding unit 140A of FIG. 1.
Referring to FIG. 2C, the first state holding unit 140A includes three flip-flops 142, 144 and 146. The flip-flops 142, 144 and 146 receive respective bits of the lagging sum signal SUM_LATE<0:2> to output the respective lagging information signals LATE_COM<0:2> in response to the reference clock REF.
Although not shown in detail, the leading digital filter 100B includes a leading adder 120B, a second state holding unit 140B, and a leading determining unit 160B. The leading adder 120B is implemented with a 3-bit adder that adds the phase leading signals PD_EARLY received for 8 periods of the reference clock REF. The second state holding unit 140B receives a leading sum signal SUM_EARLY<0:2> corresponding to an addition result of the leading adder 120B and feeds back a leading information signal EARLY_COM<0:2> to the leading adder 120B in response to the reference clock REF. When the addition of the phase leading signals PD_EARLY received for 8 periods of the reference clock REF is completed, the leading determining unit 160B outputs the leading state signal EARLY according to the leading information signal EARLY_COM<0:2>.
When the phase lagging signal PD_LATE or the phase leading signal PD_EARLY successively occurs more than a predetermined frequency for eight periods of the reference clock REF, the lagging determining unit 160A and the leading determining unit 160B determine that the respective signals are valid, and output the lagging state signal LATE or the leading state signal EARLY. The lagging state signal LATE and the leading state signal EARLY are used to control the CDR operation. For example, when one of the lagging state signal LATE and the leading state signal EARLY is activated, the CDR circuit operates according to the activated signal. When both of the lagging state signals LATE and the leading state signal EARLY are activated, the CDR circuit holds the current state without further adjustment.
Although it has been described in the above embodiment that the digital filter 100 outputs the lagging state signal LATE and the leading state signal EARLY with respect to eight periods of the reference clock REF, the present invention is not limited thereto. For example, if the digital filter 100 operates on the basis of 16 periods, the digital filter 100 may be implemented with a larger number of the adders and flip-flops in the lagging and leading adders 120A and 120B, and the first and second state holding units 140A and 140B respectively.
In the CDR circuit, the digital filter 100 for filtering the comparison results outputted from the phase comparator 110 in order to output the lagging state signal LATE and the leading state signal EARLY is implemented with a plurality of adders and a plurality of flip-flops as described above. Such an implementation demands a lot of transistors, resulting in increase in a size of the CDR circuit. That is, the digital filter 100 will occupy a large area in the semiconductor memory device.
As the integration density of semiconductor memory devices increases, many efforts have been made to scale down a peripheral region controlling and executing the data input and output as well as a core region including a plurality of cells storing data. However, since the conventional digital filter occupies a very large area, there is a limitation in adopting it in the high-integration semiconductor memory device. Further, even though the conventional digital filter is adopted, it will impose a significant burden on a design of the high-integration semiconductor memory device.